1. Field of the Invention
This invention relates to a semiconductor memory apparatus, and more particularly to a semiconductor memory apparatus suitably used to operate SCR type memory cells at a high speed.
2. Description of the Prior Art
An SCR type memory cell shown in FIG. 1 is conventionally employed as a memory cell for storing information therein. It is formed from a pair of pnp transistors and a pair of double emitter transistors, and one of the two emitters of each of the double emitter transistors is connected to a terminal 2. When the SCR type memory cell is used in a selecting circuit, the terminals 2 are connected individually to bit lines BL1 and BL2 represented by short dash lines in FIG. 1.
A typical memory cell selecting circuit which is constituted using conventional SCR type memory cells is shown in FIG. 2. Referring to FIG. 2, since generally a large number of memory cells (loads) are assigned to each word selecting line UWL, the access time to a memory cell can be decreased to raise the throughput by decreasing the amplitude between the select and deselect word lines. The case is considered now where the first memory cell 11 connected to a word selecting line UWL1 is in a selected condition, the second memory cell 12 connected to another word selecting line UWL2 is in a deselected condition, the memory cells 11 and 12 have internal voltage values shown in FIG. 2.
As shown in FIG. 2, the voltage value of the word selecting line UWL1 is -2 Vf.perspectiveto.-1.6 volts; the voltage value of the low side of the first memory cell 11 is -3 Vf.perspectiveto.-2.4 volts; and the voltage value of the high side of the first memory 11 is -2 Vf.perspectiveto.-1.6 volts, the voltage value of the word deselecting line UWL2 is -2 Vf-1.1 volts.perspectiveto.-2.7 volts; the voltage of the low side of the second memory cell 12 is -3 Vf-1.1 volts.perspectiveto.-3.5 volts; and the voltage value of the high side of the second memory 12 is -2 Vf-1.1 volts.perspectiveto.-2.7 volts.
Normally, the amplitude between the select and deselect word selecting lines UWL is determined by the low side voltage value of a selected memory cell and the high side voltage value of a deselected memory cell. For example, when the base potential of a transistor Q1 which is the holding node of the selected memory cell in FIG. 2 is low and the base potential of transistor Q3 which is the holding node of the deselected memory cell is high, the word selecting line amplitude is 1.1 volts.
In this case, the base potential of transistor Q1 is equal to the low side voltage value=-3 Vf.perspectiveto.-2.4 volts while the base potential of transistor Q3 is equal to the high side voltage value=-2 Vf-1.1 volts.perspectiveto.-2.7 volts, and the potential of the low side of the selected memory cell is higher than the potential of the high side of the deselected memory cell. Consequently, upon writing write current flows from the emitter of the transistor Q1 so that the transistor Q1 is turned from off state to an on state, thereby to allow normal writing of data.
If the word selecting line amplitude is set, for example, to 0.6 volts in order to realize higher throughput with such a selecting circuit as described, the base potential of the transistor Q1 is equal to the low side voltage value=-3 Vf.perspectiveto.-2.4 volts and the base potential of the transistor Q3 is equal to the high side base potential=-2 Vf-0.6 volts.perspectiveto.-2.2 volts. Consequently, the potential of the high side of the deselected memory cell is higher than the potential of the low side of the selected memory cell. As a result, the write current does not flows not from the emitter of the transistor Q1 which is a target upon such writing but flows from the emitter of the deselected transistor Q3. Therefore, there is a potential problem that, if the amplitude between word selecting lines is reduced in order to realize higher throughput, then a write error may occur in this manner.
From the above discussions, when such a conventional SCR type memory cell as described above is employed, the word selecting line amplitude must be at least higher than 1.1 volts, including a mergin of about 0.3 volts (0.8 volts+0.3 volts=1.1 volts) taking dispersion and other factors into consideration. This results in increase of time required for selection of a memory cell and hence in increase of access time, which is disadvantageous for the memory apparatus.
Furthermore, since write/read bit lines are common, current values upon reading and writing must be set to individually suitable set values while the write side bit line voltage is low at -4 Vf (.perspectiveto.-3.2 volts). Designing a peripheral circuit which operates on a power supply voltage of (4 Vf-V.sub.EE) for writing and reading operations is difficult.
Also, when data are to be written into a selected memory cell, transistor Q1 must be turned from an off to on state as described above and the emitter potential of the transistor Q1 must be lowered below -4 Vf.perspectiveto.-3.2 volts. This makes it very difficult to construct a write controlling circuit which operates on very low power voltage supply, when the emitter potential of the transistor Q1 is low.